The present invention relates to a method for manufacturing a semiconductor device; and, more particularly, to a method for manufacturing a semiconductor device having a capacitor structure.
As is well known, a dynamic random access memory (DRAM) with a memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
To meet the demand, therefore, there have been proposed several methods, such as a trench type or a stack type capacitor, which is arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.
In attempt to meet the demand, there have been introduced a semiconductor device incorporated therein a high K dielectric, e.g., Ta2O5, SBT (SrBiTaOx), PZT (PbZrTiOx) or the like, as a capacitor thin film in place of conventional silicon oxide film and/or silicon nitride film.
In case when a multi-level process (not shown) is applied to the above-described semiconductor device, an inter-metal dielectric (IMD) layer, e.g., made of SiO2, must be formed on top of a metal interconnection by using a plasma CVD for the purpose of the insulation between each metal layer. Since the plasma CVD utilizes silane (SiH4) as a source gas, the atmosphere for forming the IMD layer becomes a hydrogen rich atmosphere, and in this step, the silicon substrate is annealed at 400xc2x0 C.
Therefore, the hydrogen gas generated by the plasma CVD process damages a capacitor thin film and a top electrode incorporated thereinto during the annealing process. That is, the hydrogen gas penetrates to the top electrode, further reaches to the capacitor thin film and reacts with oxygen atoms constituting the high K dielectrics of the capacitor thin film.
Furthermore, after the multi-level process, a passivation layer, e.g., made of SiO2, is formed thereon by using a plasma CVD. This process also has a hydrogen rich atmosphere. Therefore, the hydrogen gas generated by the passivation process also damages the capacitor structure.
These problems, therefore, tend to make it difficult to obtain the desired reproducibility, reliability and yield.
It is, therefore, an object of the present invention to provide a method for manufacturing a semiconductor device incorporating a hydrogen barrier layer therein to prevent a capacitor thin film from a hydrogen damage which is caused by a plasma chemical vapor deposition (CVD) during the formation of a passivation layer.
In accordance with one aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of:
a) preparing an active matrix provided with a transistor and an insulating layer formed around the transistor;
b) forming a capacitor structure on top of the insulating layer, wherein the capacitor structure includes a capacitor thin film made of a material having a high dielectric constant;
c) forming an intermediate dielectric (IMD) layer on top of the capacitor structure;
d) forming a Ti1-xAlxN layer on the IMD layer; and
e) carrying out a heat treatment in the presence of a gas containing oxygen, thereby converting the Ti1-xAlxN layer into a TiO2 layer and an Al2O3 layer formed on the TiO2 layer for preventing the capacitor structure from hydrogen damages.